Glossary

DRAM in general

Types of DRAM
Speed of DRAM

Module

Memory module
TCP
SPD
x64-bit/x72-bit(Configuration of Memory module)
ECC
Registered module/Unbuffered module

Operating frequency, CAS latency (CL)

CAS latency (CL)
Relationship between operating frequency and CAS latency

Refresh

Self-refresh
Refresh cycle

DRAM in general

Types of DRAM

FPM (Fast Page Mode) DRAM
Asynchronous DRAM.
DRAM with high-speed access function called fast page mode.
EDO (Extended Data Out) DRAM
Asynchronous DRAM.
DRAM with high-speed access function called EDO. (DRAM designed for higher access speed during read, by extending the data output timing through the fast page mode)

Synchronous DRAM (SDRAM)
Clock-synchronous DRAM.
Memory operation is controlled through commands.
There are the following 3 types of SDRAM, which differ in their power supply voltage, pre-fetch operation, etc.

	SDR	DDR	DDR2
External clock	66 to 133MHz	100 to 200MHz	200 to 400MHz
Data transfer speed	66 to 133Mtps	200 to 400Mtps	400 to 800Mtps
Power supply voltage	3.3V	2.5V	1.8V
Prefetch	1	2	4
Burst length	1, 2, 4, 8, full page	2, 4, 8	4, 8
Package	TSOP	TSOP	BGA

RDRAM (Rambus DRAM)
High-speed DRAM that uses the Rambus high-speed interface technology developed by Rambus, Inc. (US). The reduction in the number of signal lines enables high-speed operation. The data transfer speed is 600 to 1200 Mega transfers per second (Mtps).

Speed of DRAM

The standard systems differ depending on whether the DRAM is implemented as a component or as a memory module.
Furthermore, DRAM comprises a number of different types, i.e. SDR SDRAM, DDR SDRAM, and RDRAM.

SDRAM

Category	Spec.	External Clock	Data Transfer Speed
Component	PC66	66MHz	66Mtps
	PC100	100MHz	100Mtps
	PC133	133MHz	133Mtps
Module	PC66	66MHz	500MB/s
	PC100	100MHz	800MB/s
	PC133	133MHz	1GB/s

DDR

Category	Spec.	External Clock	Data Transfer Speed
Component	DDR200	100MHz	200Mtps
	DDR266	133MHz	266Mtps
	DDR333	166MHz	333Mtps
	DDR400	200MHz	400Mtps
Module	PC1600	100MHz	1.6GB/s
	PC2100	133MHz	2.1GB/s
	PC2700	166MHz	2.7GB/s
	PC3200	200MHz	3.2GB/s

DDR2

Category	Spec.	External Clock	Data Transfer Speed
Component	DDR2-400	200MHz	400Mtps
	DDR2-533	266MHz	533Mtps
	DDR2-667	333MHz	667Mtps
	DDR2-800	400MHz	800Mtps
Module	PC2-3200	200MHz	3.2GB/s
	PC2-4300	266MHz	4.3GB/s
	PC2-5400	333MHz	5.4GB/s
	PC2-6400	400MHz	6.4GB/s

RDRAM

Category	Spec.	External Clock	Data Transfer Speed
Component	PC600	300MHz	600Mtps
	PC800	400MHz	800Mtps
	PC1066	533MHz	1066Mtps
	PC1200	600MHz	1200Mtps
Module		300MHz	2.4GB/s (2ch)
		400MHz	3.6GB/s (2ch)
		533MHz	4.2GB/s (2ch)
		600MHz	4.8GB/s (2ch)

Module

Memory module: A DRAM chip packaged in TSOP, TCP, etc., is called "component", and its capacity is normally described in "bit" units.
By contrast, a memory module consists of several DRAM components mounted on a board, allowing easy mounting in a PC, etc. The capacity of a memory module is normally described in "Byte" (= 8 bits) units.
TCP: Normally in TSOPs, the chip is completely sealed with resin, whereas in the case of TCP (Tape Carrier Package), the chip is placed on a tape with its reverse face exposed. Elpida's TCP is an original Elpida package technology specially designed for modules, which enables stacking without increasing the module profile.

Photo: High-density module implemented with TCP stacking
SPD: SPD, which stands for Serial Presence Detect, is also called serial PD. It consists of serial (1-bit I/O) EEPROM, and contains memory module specification information such as the DRAM type, capacity, and access speed. On the PC side, by reading the SPD, it is possible to automatically set the appropriate timing for the module in question.
For the data stored in the SPD of particular products, please refer to Serial PD Matrix in the product data sheet.
x64-bit/x72-bit(Configuration of Memory module): 72-bit configuration memory modules are an ECC-compliant memory module. This is a configuration in which redundant bits (8 bits) capable of error corrections have been added to the regular data bus width (64 bits).
ECC: ECC stands for Error Correction Code. This is a function capable of correcting errors while checking for data errors in memory.
Concretely, ECC is "send data" that includes redundant bits capable of detecting the existence of errors that occur during transfer at the side that receives the data, and it is capable of restoring the data to the original correct data based on given rules.
Registered module/Unbuffered module: A registered module is a memory module that performs data transfer via registers on the memory module.
Since the address and command signals are stored once to the registers so they can be output all at the same time in synchronization with the PLL, stable signal transmission is possible even if the number of components added to the module increases. Thus, registered modules are ideal for servers and workstations that require large capacities and high reliability. By contrast, unbuffered modules use a configuration without the registers described above, and they are used mainly in PCs.

Operating frequency, CAS latency (CL)

CAS latency (CL)

The CAS latency indicates the number of clocks required after a column address is given until the data is read. When CL = 2, the data is output 2 clocks later, and when CL = 3, it is output 3 clocks later.

Relationship between operating frequency and CAS latency

Even for the same product, the CAS latency differs according to the operating frequency that is used.
For example, assuming SDRAM for which 20ns is required until the data is read out after its address is given:

If operating frequency = 100MHz (1 clock = 10.0ns)
>> operation with CAS latency = 2 (CL = 2) results.
If operating frequency = 133MHz (1 clock = 7.5ns)
>> operation with CAS latency = 3 (CL = 3) results.

For the relationship between the operating frequency and CAS latency of particular products, please refer to Relationship Between Frequency and Minimum Latency in the data sheet.

Refresh

Self-refresh: The self-refresh operation deactivates the clock to reduce the power consumption of the device, and it automatically executes a refresh operation by using the internal refresh counter. The self-refresh mode is effective when not accessing the device for a long time, although the data must be held.
Refresh cycle: The refresh cycle rules are written as 8,192/64ms (or 8K/64ms), for example. This means that 8,192 refresh cycles must be performed within 64ms to hold the data in the memory cells.