Elpida Memory Develops World's Fastest Data Rate Technology for DDR2 SDRAM
Breakthrough Technologies Enable High Speed with Low Voltage Operation
TOKYO, JAPAN, June 17, 2002 - Elpida Memory, Inc. (Elpida), announced today the development of new circuit technologies and a low-impedance hierarchical I/O architecture that enables 1 Gigabit per second (Gbps) per pin operation with a 1.8 Volt (V) power supply in a multi-Gb DRAM. The results were verified with a 0.13 micron 512 Megabit DDR2 SDRAM, and represent performance that is 7.5 times that of Single-Data-Rate PC133 SDRAM, and a 75% improvement over DDR 266. On June 14, Elpida Memory presented two papers on these technologies at 2002 symposium on VLSI Circuits in Honolulu, Hawaii.
To achieve 1 Gbps data rates at 1.8 V requires precisely synchronized regenerated clocking with less than 30 ps misalignment, and high-integrity output data signals for a maximized valid data window. Such performance also requires a read/write cycle time of less than 4 ns and an access time of less than 8 ns. Elpida's unique technology satisfies these requirements, providing more than enough bandwidth for high-end workstations and PCs that require the maximum 533 Mbps operation specified by DDR2 at 1.8 V. The technology will also accommodate the highest data rates of the next-generation DRAM specification, DDR3.
"By combining both high-speed and low-voltage operations, Elpida's advanced technologies and architectures are driving memory bandwidth to never-before-seen levels," said Jun Kitano, director of Technical Marketing for Elpida Memory (USA) Inc. "As a result, Elpida customers will experience the world's fastest data rates to accommodate the high-end systems of today as well as the DDR3 implementations of tomorrow."
Elpida combines the highest performance device and process technologies with advanced new circuit technologies that meet the challenges of next generation DRAM technologies:
- Output Skew Control: to eliminate output skew caused by device characteristics, operation voltage, and temperature fluctuations, Elpida has developed:
- Low-power, high-resolution digital delay-locked-loop (DLL): Includes clock regeneration circuits to align the output data timing with the input clocking at 1.6 V operation or lower.
- Output buffer circuit: Adjusts the output buffer impedance while maintaining the slew rate of output signals. These new circuits can reduce the output skew to as low as 10 ps, enabling the component to realize its potential of 1 Gbps.
- Reduced Cycle and Access Time: To reduce read/write cycle time and access time, Elpida has designed a new architecture that includes:
- Low-impedance hierarchical I/O architecture that calls for routing divided I/O lines over the memory cells with no tightening of the wiring pitch. This reduces the load of I/O lines by 50% and enables a 2.2 ns reduction of the read/write cycle time.
- Distributed data transfer scheme prioritized by ordered data. The new architecture achieves 4 ns read/write cycle time, which is a 45% reduction in access time to accommodate the 1 Gbps data rate of the DDR2 architecture.
The design of computer systems is constantly improving both in terms of performance and power consumption, and 1.8 V DDR2 SDRAM is a necessary solution for the main memory component of these systems. Elpida's new circuit technologies can be used to fabricate the world's first commercial DDR2 SDRAM from Elpida and will hasten the development of next-generation DDR2I specifications into the mainstream of DRAM applications.
Papers
- 1-Gb/s/pin 512-Mb DDR2 SDRAM using a digital DLL and a slew-rate-controlled output buffer
(PDF: 388KB) - 1-Gb/s/pin Multi-Gigabit DRAM Design with Low Impedance Hierarchial I/O Architecture
(PDF: 107KB)
About Elpida Memory, Inc.
Elpida Memory, Inc. is a technology leader in Dynamic Random Access Memory (DRAM) with headquarters based in Tokyo, Japan, and sales and marketing operations located in Japan, North America, Europe and Asia. Elpida offers a broad range of leading-edge DRAM products including RDRAM®, SDRAM, DDR SDRAM, Mobile RAM and Consumer SDRAM. Device densities currently range up to 512 Megabits each, and Module (DIMM) densities range up to 2 Gigabytes each. Elpida offers a variety of standard and high performance packaging techniques, including TSOP, BGA, FBGA, Tape Carrier Package (TCP), and Double Density Package (DDP). Elpida's research, design and development operations were merged from NEC and Hitachi on April 1, 2000 and sales and marketing operations commenced in Q1, 2001. Elpida's main DRAM foundries are located at NEC Hiroshima and Hitachi Nippon Steel Semiconductor Singapore. Elpida's own 300 mm DRAM wafer manufacturing facility is scheduled to begin production by January 2003.
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