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TOKYO, March 13, 2003 - Elpida Memory (Elpida), Inc. today announced the availability of its 128 Megabit (4 Million words x 32-bits) DDR2 SDRAM devices for notebook and desktop PC graphics applications. The new devices offer high speed, low power and enhanced thermal characteristics that enable them to perform in the constrained environments often experienced by mobile applications. The devices incorporate "GDDR2-M" technology, featuring an innovative low-power termination scheme and a new data inversion technology that was jointly developed with ATI Technologies, Inc. to speed operation and reduce power consumption.
"We are very excited about the outcome of our joint development efforts with ATI," said Jun Kitano, director of Technical Marketing at Elpida Memory. "The close cooperation of our two companies created the synergy to develop products that bring desktop PC-class graphics performance to notebook platforms."
"The implications of GDDR2-M technology for notebook users are huge," said Joe Macri, Director of Technology, ATI Research Silicon Valley. "GDDR2-M will allow ATI to blast right through the current ceiling on memory speeds. We'll fly past 300 MHz and still minimize power consumption. As the joint developer of this technology, we'll be the first to market, extending our leadership in mobile performance and battery life even further."
GDDR2-M Technology is Optimized for High-Speed Graphics
The new x32 DDR2 SDRAM devices have been optimized for graphics applications using the "GDDR2-M" technology. The design is based on the standard DDR2 SDRAM architecture, with enhanced On-Die Termination (ODT) and new data inversion technology.
Data Inversion Technology Reduces Noise and Power Consumption by 50%
Data inversion technology is a hardware design technique that was jointly developed by both Elpida Memory and ATI Technologies, and it has been incorporated into both the memory device and the Visual Processing Unit (VPU) devices. This technology alters the pattern of data that flows between the memory and VPU to minimize data flipping (switching). Data flipping occurs during approximately fifty percent of all data transfers, and this is a common source of noise and power consumption of high-speed data busses. The end result of incorporating this new data inversion technology is a wide, valid data bus with fifty percent less noise and lower power versus devices that do not use this technology.
Enhanced On-Die-Termination Reduces System Costs and Power Consumption
On-Die-Termination (ODT) will be widely adopted in the conventional DDR2 SDRAM architecture, because it helps to create a clean signal during high speed data transmissions. Elpida's enhanced ODT used in GDDR2-M is different from that used in standard DDR2 SDRAM in that it is a 'pull-down' type self-termination that works effectively with the high-speed, point-to-point interface used in graphics. This version of ODT minimizes the direct current (DC) power at the termination circuit. As a result, graphics systems can reduce the size of the board, and consequently the system cost. This is an ideal implementation for mobile graphics systems where high-speed is necessary, but power and space are both very precious resources.
High Bandwidth, Low Power Features
Elpida's new 128 Megabit DDR2 SDRAM devices are organized as 1,048,576 words x 32 bits x 4 banks. The three new devices (DC0122A-35, DC0122A-40, DC0122A-45) are available now in sample quantities in 350, 400 and 450 MHz versions to match the performance of the latest VPUs, delivering high-bandwidth performance of 700, 800 or 900 Megabits per second (Mbps) respectively. Using Elpida's proven 0.13 micron process technology, the new devices offer low-voltage operation (VDDQ = 1.8V, VDD = 2.5V) as well as low memory power consumption (only 1.7 Watts for the 350 and 400 MHz versions) which is particularly important for notebook computers. The new devices have burst read/write operation, a burst length (BL) of 4, and sequential burst sequences. Data strobes (DQS) for both read and write are available, resulting in reliable, high-speed bus designs. The devices operate with a fixed / CAS latency (CL) of 6. They also have 4096 refresh cycles: 7.8 micros (4096 rows/32ms) and implement both auto refresh and self refresh. The packaging is standard 144-ball FBGA.
Availability
| Part Number |
Description |
Clock
Frequency |
Availability |
| DC0122A-35 |
128 Megabit (4M Words x 32-bit x 4 banks);
DDR SDRAM device w/ ODT and Data Inversion;
144-ball FBGA package |
350 MHz |
Samples: Now
Volume: Q2, 2003 |
| DC0122A-40 |
128 Megabit (4M Words x 32-bit x 4 banks);
DDR SDRAM device w/ ODT and Data Inversion;
144-ball FBGA package |
400 MHz |
Samples: Now
Volume: Q2, 2003 |
| DC0122A-45 |
128 Megabit (4M Words x 32-bit x 4 banks);
DDR SDRAM device w/ ODT and Data Inversion;
144-ball FBGA package |
450 MHz |
Samples: Now
Volume: Q3, 2003 |
About Elpida Memory, Inc.
Elpida Memory, Inc. is a technology leader in Dynamic Random Access Memory (DRAM) with headquarters based in Tokyo, Japan, and sales and marketing operations located in Japan, North America, Europe and Asia. Elpida offers a broad range of leading-edge DRAM products including RDRAM®, SDRAM, DDR SDRAM, Mobile RAM and Consumer SDRAM. Device densities currently range up to 512 Megabits each, and Module (DIMM) densities range up to 2 Gigabytes each. Elpida offers a variety of standard and high performance packaging techniques, including TSOP, BGA, FBGA, Tape Carrier Package (TCP), and Double Density Package (DDP). Elpida's research, design and development operations began as a joint venture between NEC and Hitachi on April 1, 2000, and sales and marketing operations commenced in Q1, 2001.
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