<Technical Document>
Technology #1:
High-Speed DRAM for Advanced Network Routers and High-Performance Servers
Overview
Developed in cooperation with Hitachi, Ltd., Elpida's new high-speed DRAM technology accelerates route-finding in network routers and cache memory applications in servers. The technology incorporates high-speed memory arrays that use two memory cells per bit called "twin-cell memory", along with a high-speed data amplification method called "three-stage sensing". Because the same fabrication process is used as with general-purpose DRAM, the performance benefits of this technology can be realized at a relatively low cost.
Background
As the Internet continues to expand, there has been a corresponding increase in communication speeds and traffic along network backbones. In order to rapidly process these huge amounts of high-speed data, routing equipment must offer ever-higher performance in its management of network flow. This in turn requires faster and larger-capacity memory subsystems. At the same time, cache memory capacities are growing rapidly as multithread and multi-core CPU configurations are increasingly used for servers. Although general-purpose DRAMs offer large capacity, their slow random access time of 20 ns to 60 ns makes them poorly suited for the requirements of high-performance servers, much less routers that support high-speed optical communications and IPv6. Fast SRAM offers the necessary speed, but its high price makes it unfeasible as a large-capacity solution.
Purpose and Focus
To face these issues, Elpida and Hitachi worked together to develop high-speed DRAM technology with an accelerated random access time that is 1/3 to 1/10 that of conventional DRAM, while using a general-purpose DRAM process. Modifying the small-signal amplifier design, which has been a bottleneck for higher random access speed in general-purpose DRAM, and incorporating a new type of memory cell array with a high-sensitivity amplifier achieved this. The characteristics of the newly developed technologies are as follows:
- Twin-cell memory: The twin-cell memory configuration uses the same memory cells as those of general-purpose DRAM, but uses two cells per bit, and reads and writes data signals on a complementary basis. This doubling of the read signal amount, combined with the complementary operation, eliminates imbalances and noise and enables high-speed random access. Because the technology uses the same memory cell arrays as general-purpose DRAM, a new memory cell selection control method was devised.
- Three-stage sensing: In general-purpose DRAM, signals read from memory cells are first amplified by a sense amplifier and then further amplified by a main amplifier before they are output. The new Elpida method uses an ultra-high-sensitivity main amplifier configured in three stages. The combination of this amplifier and the twin-cell memory allows signal amplification without the need for a sense amplifier, thereby enabling an access time comparable to that of ultra fast SRAM.
Achievements
Based on these technologies, a 144 Megabit prototype was fabricated and evaluated using Elpida's original 0.11 um DRAM process for general-purpose DRAM. The random access time was verified to be 6 ns or lower, which provides a sufficient operating margin, and confirms the probability that a random access time of 4.8 ns could be achieved with some additional tuning. Moreover, through the use of an architecture that allows simultaneous access of I/O ports by making them independent, a high data rate of 6 Gigabytes per second was also achieved.
Technology #2:
Mass-Produced 1 Gigabit DRAM Circuit Technology Enabling DDR1/DDR2 on a Single Chip
Overview
Elpida has developed a high-speed circuit technology for 1 Gigabit DDR1/DDR2 mixed chips that combine high capacity with a high-speed data rate, and are ideal as the main memory for servers and high-end PCs. The speed factor was achieved by taking advantage of the regularity of the external input commands of DDR2, resulting in an input logic circuit that does not require an excessive timing margin. Large capacity was achieved through the use of a circuit type that minimizes the layout area without sacrificing access speed, thereby allowing the combination of DDR1 and DDR2 on a single chip. The result is that a single 1 Gigabit DRAM can offer high-speed operation of 400 Mbps for DDR1 and 800 Mbps for DDR2, making it possible to offer large-capacity, high-speed memory for servers and high-end PCs.
Background
Fast DRAMs based on the DDR1 and DDR2 specifications were developed to fill the need for faster main memory to accommodate ever-rising processor clock frequencies. DDR1 and DDR2 are currently in a transitional stage in the field of servers and high-end PCs, hence there is a demand for timely development and supply of various types of DRAMs to support evolving needs.
Purpose and Focus
To meet these requirements in developing 1 Gigabit DRAMs, Elpida worked to develop a circuit that supports DDR1 and DDR2 on the same chip through interconnect layer switching. Such a design makes it possible to flexibly determine the DDR1/DDR2 option according to market requirement trends.
To accommodate two types of DRAM with different data rates on the same chip, Elpida developed an input latch circuit with an internal clock frequency that is double the input clock frequency for DDR2. Moreover, Elpida sought to use the same elements for the output buffer circuit and succeeded in minimizing the layout area overhead. The main features of the newly developed technology are as follows:
- Input latch circuit with an internal clock frequency that is double the input clock frequency: The same DDR2 commands (such as ACTV, READ, WRITE) cannot be issued continually with the external clock. Instead, they are output to the same device only once every 2 clocks at the fastest. Taking this into account, Elpida developed a method that controls the command input latch circuit using an internal clock that is double the input clock frequency. There are actually two internal clock systems, differentiated by their phase, which differs by one external clock cycle, and commands issued by either clock can be captured. The result is a circuit that has sufficient operating margin for the DDR2 clock with the smallest period (2.5 ns) but with the same circuit configuration as the input latch block of DDR1. The measurement results show that operation is possible even with an extremely short input clock period of 2.15 ns.
- Common output buffer circuit for DDR1 and DDR2: As DDR1 and DDR2 use different external voltages (2.5 V and 1.8 V), device selection for the common parts of the output buffer circuit directly driven by the external voltage was problematic. Since DDR1 uses a high external output voltage, it was not possible to use low-voltage high-speed devices with a thin gate oxide film. On the other hand, using an output circuit for DDR2 with a thick oxide film and a design that emphasizes the withstanding voltage used for DDR1 is problematic in terms of the necessary increase in layout area and the accompanying increase in output capacitance, thus restricting the devices that can be used. Furthermore, in the case of DDR2, in order to realize a high output current driving capability and fast data rate in the memory system even at a low voltage, On Die Termination (ODT) and Off-Chip Driver (OCD) impedance adjustment functions must be mounted, which has a major impact on the layout area and the potential for a space-saving design. These challenges were met by maximizing the use of devices with a thick oxide film used in DDR1 output buffer circuits in DDR2 output buffer circuits, and optimizing the combination with thin gate oxide film devices that are used only in DDR2 output circuits. This minimized the layout area and output capacitance while achieving the fast data rate required for DDR2.
Achievements
Testing and evaluation of a 1 Gigabit DRAM fabricated using a 0.10 (m process based on these technologies showed that a clock cycle of 2.15 ns can be realized even under the worst external power supply conditions, and that high-speed operation of 400 Mbps for DDR1 and 800 Mbps for DDR2 can be obtained with a high yield. Moreover, the increase in layout area was successfully kept within 0.3% by integrating DDR1 and DDR2 on the same chip.
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Information in this news release is current as of the timing of the release, but may be revised later without notice.