EBE10UE8AFSA

Specifications

Density: 1GB
Organization
-128M words x 64 bits, 1 rank
Mounting 8 pieces of 1G bits DDR2 SDRAM with FBGA
Package: 200-pin socket type small outline dual in line memory module (SO-DIMM)
-PCB height: 30.0mm
-Lead pitch: 0.6mm
-Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD = 1.8V +/- 0.1V
Data rate: 800Mbps/667Mbps (max.)
Four internal banks for concurrent operation (components)
Interface: SSTL_18
Burst lengths (BL): 4, 8
/CAS Latency (CL): 3, 4, 5, 6
Precharge: auto precharge option for each burst access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
-Average refresh period
7.8 µs at 0'C <= TC <= +85'C
3.9 µs at +85'C < TC <= +95'C
Operating case temperature range
-TC = 0'C to +95'C

Double-data-rate architecture; two data transfers per clock cycle
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe operation

Part Number	Grade	Package	Datasheet	IBIS	Verilog
EBE10UE8AFSA-8G-F	PC2-6400(6-6-6)	84-FBGA	E1450E20	TBD