EBE82AF4A1RA

Specifications

Density: 8GB
Organization
-1024M words x 72 bits, 4 ranks
Mounting 36 pieces of 2G bits DDR2 SDRAM with DDP (FBGA)
-DDP: 2 pieces of 1Gb chips sealed in one package
Package: 240-pin socket type dual in line memory module (DIMM)
-PCB height: 30.0mm
-Lead pitch: 1.0mm
-Lead-free (RoHS compliant)
Power supply: VDD = 1.8V +/- 0.1V
Data rate: 667Mbps/533Mbps (max.)
Eight internal banks for concurrent operation (components)
Interface: SSTL_18
Burst lengths (BL): 4, 8
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
-Average refresh period
7.8 µs at 0'C <= TC <= +85'C
3.9 µs at +85'C < TC <= +95'C
Operating case temperature range
-TC = 0'C to +95'C

Double-data-rate architecture; two data transfers per clock cycle
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Posted /CAS by programmable additive latency for better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe operation
1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2K bits EEPROM) for Presence Detect (PD)

Part Number	Grade	Package	Datasheet	IBIS	Verilog
EBE82AF4A1RA-6E-E	PC2-5300(5-5-5)	DDP	E1166E10	TBD
EBE82AF4A1RA-5C-E	PC2-4200(4-4-4)	DDP	E1166E10	TBD