EBE82FF4A1RQ

Specifications

• Density: 8GB
• Organization
  -1024M words x 72 bits, 4 ranks
• Mounting 36 pieces of 2G bits DDR2 SDRAM with DDP (FBGA)
  -DDP: 2 pieces of 1Gb chips sealed in one package
• Package
  -240-pin fully buffered, socket type dual in line memory module (FB-DIMM)
    PCB height: 30.35mm
    Lead pitch: 1.0mm
  -Advanced Memory Buffer (AMB): 655-ball FCBGA
  -Lead-free (RoHS compliant)
• Power supply
  -DDR2 SDRAM: VDD = 1.8V +/- 0.1V
  -AMB: VCC = 1.5V +0.075V/-0.045
• Data rate: 667Mbps
• Eight internal banks for concurrent operation (components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
  -Average refresh period
   7.8 µs at 0'C <= TC <= +85'C
   3.9 µs at +85'C < TC <= +95'C
• Operating case temperature range
  -TC = 0'C to +95'C

Features

• JEDEC standard Raw Card D Design
• Industry Standard Advanced Memory Buffer (AMB)
• High-speed differential point-to-point link interface at 1.5V (JEDEC spec)
  -14 north-bound (NB) high speed serial lanes
  -10 south-bound (SB) high speed serial lanes
• Various features/modes:
  -MemBIST and IBIST test functions
  -Transparent mode and direct access mode for DRAM testing
  -Interface for a thermal sensor and status indicator
• Channel error detection and reporting
• Automatic DDR2 SDRAM bus and channel calibration
• SPD (serial presence detect) with 1 piece of 256 byte serial EEPROM

Ordering Information

User's Manual, Technical Note

• HOW TO USE DDR2 SDRAM - User's Manual (PDF: 491KB)
• New Function of DDR2 SDRAM On Die Termination (ODT) - TN (PDF: 212KB)
• New Function of DDR2 SDRAM Off-Chip Driver (OCD) - TN (PDF: 147KB)
• DDR2 SDRAM TECHNOLOGY - TN (PDF: 51KB)

• MODULE HANDLING GUIDE - TN (PDF: 506KB)