EBJ41UF8BAS0

Specifications

Density: 4GB
Organization
– 512M words x 64 bits, 2 ranks
Mounting 16 pieces of 2G bits DDR3 SDRAM sealed in FBGA
Package: 204-pin socket type small outline dual in line memory module (SO-DIMM)
– PCB height: 30.0mm
– Lead pitch: 0.6mm
– Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD = 1.5V ± 0.075V
Data rate: 1333Mbps/1066Mbps (max.)
Eight internal banks for concurrent operation (components)
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
/CAS Latency (CL): 6, 7, 8, 9, 10, 11
/CAS write latency (CWL): 5, 6, 7, 8
Precharge: auto precharge option for each burst access
Refresh: auto-refresh, self-refresh
Refresh cycles
– Average refresh period
7.8 µs at 0°C ≤ TC ≤ +85°C
3.9 µs at +85°C < TC ≤ +95°C
Operating case temperature range
– TC = 0°C to +95°C

Double-data-rate architecture; two data transfers per clock cycle
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for better command and data bus efficiency
On-Die-Termination (ODT) for better signal quality
– Synchronous ODT
– Dynamic ODT
– Asynchronous ODT
Multi Purpose Register (MPR) for temperature read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset function
SRT range:
– Normal/extended
Programmable Output driver impedance control

Part Number	Grade	Package	Datasheet	IBIS	Verilog
EBJ41UF8BAS0-DJ-F	PC3-10600(9-9-9)	78-FBGA	E1545E20	TBD
EBJ41UF8BAS0-AE-F	PC3-8500(7-7-7)	78-FBGA	E1545E20	TBD