EBJ51ED8BAFA

Specifications

• Density: 512MB
• Organization
  -64M words x 72 bits, 1 rank
• Mounting 9 pieces of 512M bits DDR3 SDRAM sealed in FBGA
• Package: 240-pin socket type dual in line memory module (DIMM)
  -PCB height: 30.0mm
  -Lead pitch: 1.0mm
  -Lead-free (RoHS compliant)
• Power supply: VDD = 1.5V +/- 0.075V
• Data rate: 1066Mbps/800Mbps (max.)
• Eight internal banks for concurrent operation (components)
• Interface: SSTL_15
• Burst lengths (BL): 8 and 4 with Burst Chop (BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9
• /CAS write latency (CWL): 5, 6
• Precharge: auto precharge option for each burst access
• Refresh: auto-refresh, self-refresh
• Refresh cycles
  -Average refresh period
   7.8 µs at 0'C <= TC <= +85'C
   3.9 µs at +85'C < TC <= +95'C
• Operating case temperature range
  -TC = 0'C to +95'C

Features

• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus efficiency
• On-Die-Termination (ODT) for better signal quality
  - Synchronous ODT
  - Dynamic ODT
  - Asynchronous ODT
• Multi Purpose Register (MPR) for temperature read out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset function
• SRT range:
  - Normal/extended
  - Auto/manual self-refresh
• Programmable Output driver impedance control

Ordering Information

User's Manual, Technical Note

• MODULE HANDLING GUIDE - TN (PDF: 506KB)