EDD51321CBH
- Density: 512M bits
- Organization
-x 32 bits: 4M words x 32 bits x 4 banks
- Package: 90-ball FBGA
-Lead-free (RoHS compliant)
- Power supply: VDD, VDDQ = 1.8V +0.15/-0.1V
- Data rate: 166MHz/133MHz (max.)
- 2KB page size
-Row address: A0 to A12
-Column address: A0 to A8
- Four internal banks for concurrent operation
- Interface: LVCMOS
- Burst lengths (BL): 2, 4, 8
- Burst type (BT):
-Sequential (2, 4, 8)
-Interleave (2, 4, 8)
- /CAS Latency (CL): 3
- Precharge: auto precharge option for each burst access
- Driver strength: full/half/quarter
- Refresh: auto-refresh, self-refresh
- Refresh cycles: 8192 cycles/64ms
-Average refresh period: 7.8 µs
- Operating ambient temperature range
-TA = -20'C to +85'C
- DLL is not implemented
- Low power consumption
- Double-data-rate architecture; two data transfers per clock cycle
- Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Burst termination by burst stop command and Precharge command
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