EDE1104ACSE

Specifications

Density: 1G bits
Organization
-32M words x 4 bits x 8 banks
Package: 60-ball FBGA
-Lead-free (RoHS compliant)
Power supply: VDD, VDDQ = 1.8V +/- 0.1V
Data rate: 800Mbps/667Mbps/533Mbps (max.)
1KB page size
-Row address: A0 to A13
-Column address: A0 to A9, A11
Eight internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
-Sequential (4, 8)
-Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
-Average refresh period
7.8 µs at 0'C <= TC <= +85'C
3.9 µs at +85'C < TC <= +95'C
Operating case temperature range
-TC = 0'C to +95'C

Double-data-rate architecture; two data transfers per clock cycle
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
Programmable RDQS, /RDQS output for making x 8 organization compatible to x 4 organization
/DQS, (/RDQS) can be disabled for single-ended Data Strobe operation

Part Number	Grade	Package	Datasheet	IBIS	Verilog
EDE1104ACSE-8E-E	DDR2-800(5-5-5)	60-FBGA	E0975E50	ede1104acse_110	ede1104ac_8e_0627_vp
EDE1104ACSE-6E-E	DDR2-667(5-5-5)	60-FBGA	E0975E50	ede1104acse_110	ede1104ac_6e_0627_vp
EDE1104ACSE-5C-E	DDR2-533(4-4-4)	60-FBGA	E0975E50	ede1104acse_110	ede1104ac_5c_0627_vp