EDX5116ADSE

Description

The EDX5116ADSE is a 512M bits XDR DRAM organized as 32M words x 16 bits. It is a general-purpose high-performance memory device suitable for use in a broad range of applications.

The use of Differential Rambus Signaling Level (DRSL) technology permits 4800/4000/3200 Mb/s transfer rates while using conventional system and board design technologies. XDR DRAM devices are capable of sustained data transfers of 9600/8000/6400 MB/s.

XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed memory transactions. The highly-efficient protocol yields over 95% utilization while allowing fine access granularity. The device's eight banks support up to four interleaved transactions.

It is packaged in 104-ball FBGA compatible with Rambus XDR DRAM pin configuration.

Features

• Highest pin bandwidth available
  4800/4000/3200 Mb/s Octal Data Rate (ODR) Signaling
  • Bi-directional differential RSL (DRSL)
    - Flexible read/write bandwidth allocation
    - Minimum pin count
  • On-chip termination
    - Adaptive impedance matching
    - Reduced system cost and routing complexity
• Highest sustained bandwidth per DRAM device
  • 9600/8000/6400 MB/s sustained data rate
  • Eight banks: bank-interleaved transactions at full bandwidth
  • Dynamic request scheduling
  • Early-read-after-write support for maximum efficiency
  • Zero overhead refresh
• Dynamic width control
  • EDX5116ADSE supports x16, x8 and x4 mode
• Low latency
  • 1.667/2.0/2.5 ns request packets
  • Point-to-point data interconnect for fastest possible flight time
  • Support for low-latency, fast-cycle cores
• Low power
  • 1.8V Vdd
  • Programmable small-swing I/O signaling (DRSL)
  • Low power PLL/DLL design
  • Powerdown self-refresh support
  • Per pin I/O powerdown for narrow-width operation
• Lead-free (RoHS compliant)

Ordering Information

User's Manual, Technical Note

• RECOMMENDED SOLDERING CONDITIONS & STORAGE CONDITIONS - TN (PDF: 199KB)