Features of XDR DRAM
- 4.8/4.0/3.2Gbps Octal Data Rate (ODR) signaling
4.8/4.0/3.2GHz data rate, octuple the data transfer rate of 600/500/400MHz system clock
- Bi-directional differential RSL (DRSL)
Flexible read / write bandwidth allocation
Minimum pin count
- On-chip termination
Reduced system cost and routing complexity
- 9.6GB/s (4.8E), 8.0GB/s (4.0D), 6.4GB/s (3.2A, 3.2B, 3.2C) peak data transfer rate
- 8 banks:
Bank-interleaved transactions at full bandwidth
- Dynamic request scheduling
- Early-read-after-write support for maximum efficiency
- Zero overhead refresh
|
- 1.8V VDD
- Small-swing I/O signaling (DRSL) (200mV)
- Power-down self-refresh support
- 104-ball FBGA 15.18mm x 14.56mm
- Ball-pitch 1.27mm / 0.8mm
|
XDR
| wordxbit |
Int. Banks |
Grade |
Part Number |
Class |
Supply Voltage |
Refresh Cycles |
Rev. |
Package |
Datasheet |
Simulation Model |
Product Status |
Remark |
| 32M x 16 |
8 |
4.8E |
EDX5116ADSE |
5E-E |
1.875V+/-0.075V |
16ms |
D |
104-FBGA |
E1198E20X |
|
ES |
|
| 4.0D |
4D-E |
1.8V+/-0.09V |
E1033E30 |
|
MP |
| 3.2A |
3A-E |
| 3.2B |
3B-E |
| 3.2C |
3C-E |
*Product Status: UD: Under Development, ES: Engineering Sample, MP: Mass Production, Ask: Contact Elpida sales to check the production status
|
